The SiC semiconductor device having the JFET of the trench structure is disclosed in PTL 1. The JFET disclosed in PTL 1 is configured as follows. After an n− type drift layer, a p+ type first gate region, and an n+ source region are formed on an n+ SiC substrate in the stated order, a trench is formed to penetrate those regions, and an n− type channel layer and a p+ second gate region are formed within the trench. Then, a gate electrode is formed on a surface of the second gate region, and a source electrode is formed over the gate electrode through an interlayer insulating film, and a drain electrode is formed on a rear surface of the n+ SiC substrate.
The JFET thus configured has a structure in which the trench is laid out in a strip shape. However, when the n− type channel layer epitaxially grows, both leading ends of the trench become thicker than sidewall surfaces configuring long sides of the trench, and a variation in threshold is caused. For that reason, in the JFET disclosed in PTL 1, a recess deeper than the n+ source region is formed on each leading end of the trench to eliminate the n+ type source region, so that no JFET is configured on both leading ends of the trench. As a result, the JFET is configured on only inner positions of the long sides of the trench so that the variation in threshold can be prevented, and an excess drain current can be prevented from being generated due to the variation in threshold when the gate voltage becomes closer to the threshold.